SN74HC161DR/AIP74HC161

提供SN74HC161DR/AIP74HC161中文资料_价格_PDF数据手册_引脚图

产品描述

SN74HC161DR/AIP74HC161 和74LS161都是常用的四位二进制可预置的同步加法计数器,74HC161是CMOS型,74LS161是TTL型。它可以灵活的运用在各种数字电路,以及单片机系统中实现分频器等很多重要的功能。

The AiP74HC/HCT161 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW. A LOW at the parallel enable input (P¯E¯) disables the counting action and causes the data at the data inputs (D0 to D3)to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET).

A LOW at the master reset input (M¯R¯) sets Q0 to Q3 LOW regardless of the levels at input pins CP, P¯E¯, CET and CEP (thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0.

This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula:

fmax=1/(tP(max)(CP to TC)+tSU(CEP to CP))

Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

其主要特点如下:

● Input levels:

For AiP74HC161: CMOS level

For AiP74HCT161: TTL level

● Synchronous counting and loading

● 2 count enable inputs for n-bit cascading

● Asynchronous reset

● Positive-edge triggered clock

● Specified from -40℃ to +105℃

● Packaging information: DIP16/SOP16/TSSOP16

基础参数

逻辑电路的归属系列: 74HC

逻辑类型: 二进制计数器

方向: 上

元件数: 1

单元件位数: 4

复位方式: 异步

定时方式: 同步

计数速率: 48MHz

触发器类型: 正边沿

电源电压: 2V~6V

静态电流(最大值): 8uA

不同 V,最大 CL 时的最大传播延迟: 32ns@6V,50pF

低电平输出电流(IOL): 5.2mA

高电平输出电流(IOH): 5.2mA

逻辑电平-高: 1.5V~4.2V

逻辑电平-低: 0.5V~1.8V

工作温度: -40℃~+105℃

尺寸最大值

交流参数

图1

图2

图3

功能框图

逻辑符号

IEC 逻辑符号

功能框图

逻辑框图

状态机图

时序序列图

参考报价

深圳市灵星芯微电子科技有限公司以低本高质的服务精神屹立于电子行业20多年

展开阅读全文

页面更新:2024-03-13

标签:分频器   框图   电平   最大值   计数器   符号   逻辑   参数   类型   功能

1 2 3 4 5

上滑加载更多 ↓
推荐阅读:
友情链接:
更多:

本站资料均由网友自行发布提供,仅用于学习交流。如有版权问题,请与我联系,QQ:4156828  

© CopyRight 2020-2024 All Rights Reserved. Powered By 71396.com 闽ICP备11008920号-4
闽公网安备35020302034903号

Top